removed dependency on 'readlink -f'
[rapper.git] / boards / lpc1768 / system.c
1 /******************************************************************************
2  * @file:    system_LPC17xx.c
3  * @purpose: CMSIS Cortex-M3 Device Peripheral Access Layer Source File
4  *           for the NXP LPC17xx Device Series
5  * @version: V1.1
6  * @date:    18th May 2009
7  *----------------------------------------------------------------------------
8  *
9  * Copyright (C) 2008 ARM Limited. All rights reserved.
10  *
11  * ARM Limited (ARM) is supplying this software for use with Cortex-M3
12  * processor based microcontrollers.  This file can be freely distributed
13  * within development tools that are supporting such ARM based processors.
14  *
15  * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
16  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
17  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
18  * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
19  * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
20  *
21  ******************************************************************************/
22
23
24 #include <stdint.h>
25 #include <board.h>
26
27 /*
28 //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
29 */
30
31 /*--------------------- Clock Configuration ----------------------------------
32 //
33 // <e> Clock Configuration
34 //   <h> System Controls and Status Register (SCS)
35 //     <o1.4>    OSCRANGE: Main Oscillator Range Select
36 //                     <0=>  1 MHz to 20 MHz
37 //                     <1=> 15 MHz to 24 MHz
38 //     <e1.5>       OSCEN: Main Oscillator Enable
39 //     </e>
40 //   </h>
41 //
42 //   <h> Clock Source Select Register (CLKSRCSEL)
43 //     <o2.0..1>   CLKSRC: PLL Clock Source Selection
44 //                     <0=> Internal RC oscillator
45 //                     <1=> Main oscillator
46 //                     <2=> RTC oscillator
47 //   </h>
48 //
49 //   <e3> PLL0 Configuration (Main PLL)
50 //     <h> PLL0 Configuration Register (PLL0CFG)
51 //                     <i> F_cco0 = (2 * M * F_in) / N
52 //                     <i> F_in must be in the range of 32 kHz to 50 MHz
53 //                     <i> F_cco0 must be in the range of 275 MHz to 550 MHz
54 //       <o4.0..14>  MSEL: PLL Multiplier Selection
55 //                     <6-32768><#-1>
56 //                     <i> M Value
57 //       <o4.16..23> NSEL: PLL Divider Selection
58 //                     <1-256><#-1>
59 //                     <i> N Value
60 //     </h>
61 //   </e>
62 //
63 //   <e5> PLL1 Configuration (USB PLL)
64 //     <h> PLL1 Configuration Register (PLL1CFG)
65 //                     <i> F_usb = M * F_osc or F_usb = F_cco1 / (2 * P)
66 //                     <i> F_cco1 = F_osc * M * 2 * P
67 //                     <i> F_cco1 must be in the range of 156 MHz to 320 MHz
68 //       <o6.0..4>   MSEL: PLL Multiplier Selection
69 //                     <1-32><#-1>
70 //                     <i> M Value (for USB maximum value is 4)
71 //       <o6.5..6>   PSEL: PLL Divider Selection
72 //                     <0=> 1
73 //                     <1=> 2
74 //                     <2=> 4
75 //                     <3=> 8
76 //                     <i> P Value
77 //     </h>
78 //   </e>
79 //
80 //   <h> CPU Clock Configuration Register (CCLKCFG)
81 //     <o7.0..7>  CCLKSEL: Divide Value for CPU Clock from PLL0
82 //                     <2-256:2><#-1>
83 //   </h>
84 //
85 //   <h> USB Clock Configuration Register (USBCLKCFG)
86 //     <o8.0..3>   USBSEL: Divide Value for USB Clock from PLL1
87 //                     <0-15>
88 //                     <i> Divide is USBSEL + 1
89 //   </h>
90 //
91 //   <h> Peripheral Clock Selection Register 0 (PCLKSEL0)
92 //     <o9.0..1>    PCLK_WDT: Peripheral Clock Selection for WDT
93 //                     <0=> Pclk = Cclk / 4
94 //                     <1=> Pclk = Cclk
95 //                     <2=> Pclk = Cclk / 2
96 //                     <3=> Pclk = Hclk / 8
97 //     <o9.2..3>    PCLK_TIMER0: Peripheral Clock Selection for TIMER0
98 //                     <0=> Pclk = Cclk / 4
99 //                     <1=> Pclk = Cclk
100 //                     <2=> Pclk = Cclk / 2
101 //                     <3=> Pclk = Hclk / 8
102 //     <o9.4..5>    PCLK_TIMER1: Peripheral Clock Selection for TIMER1
103 //                     <0=> Pclk = Cclk / 4
104 //                     <1=> Pclk = Cclk
105 //                     <2=> Pclk = Cclk / 2
106 //                     <3=> Pclk = Hclk / 8
107 //     <o9.6..7>    PCLK_UART0: Peripheral Clock Selection for UART0
108 //                     <0=> Pclk = Cclk / 4
109 //                     <1=> Pclk = Cclk
110 //                     <2=> Pclk = Cclk / 2
111 //                     <3=> Pclk = Hclk / 8
112 //     <o9.8..9>    PCLK_UART1: Peripheral Clock Selection for UART1
113 //                     <0=> Pclk = Cclk / 4
114 //                     <1=> Pclk = Cclk
115 //                     <2=> Pclk = Cclk / 2
116 //                     <3=> Pclk = Hclk / 8
117 //     <o9.12..13>  PCLK_PWM1: Peripheral Clock Selection for PWM1
118 //                     <0=> Pclk = Cclk / 4
119 //                     <1=> Pclk = Cclk
120 //                     <2=> Pclk = Cclk / 2
121 //                     <3=> Pclk = Hclk / 8
122 //     <o9.14..15>  PCLK_I2C0: Peripheral Clock Selection for I2C0
123 //                     <0=> Pclk = Cclk / 4
124 //                     <1=> Pclk = Cclk
125 //                     <2=> Pclk = Cclk / 2
126 //                     <3=> Pclk = Hclk / 8
127 //     <o9.16..17>  PCLK_SPI: Peripheral Clock Selection for SPI
128 //                     <0=> Pclk = Cclk / 4
129 //                     <1=> Pclk = Cclk
130 //                     <2=> Pclk = Cclk / 2
131 //                     <3=> Pclk = Hclk / 8
132 //     <o9.20..21>  PCLK_SSP1: Peripheral Clock Selection for SSP1
133 //                     <0=> Pclk = Cclk / 4
134 //                     <1=> Pclk = Cclk
135 //                     <2=> Pclk = Cclk / 2
136 //                     <3=> Pclk = Hclk / 8
137 //     <o9.22..23>  PCLK_DAC: Peripheral Clock Selection for DAC
138 //                     <0=> Pclk = Cclk / 4
139 //                     <1=> Pclk = Cclk
140 //                     <2=> Pclk = Cclk / 2
141 //                     <3=> Pclk = Hclk / 8
142 //     <o9.24..25>  PCLK_ADC: Peripheral Clock Selection for ADC
143 //                     <0=> Pclk = Cclk / 4
144 //                     <1=> Pclk = Cclk
145 //                     <2=> Pclk = Cclk / 2
146 //                     <3=> Pclk = Hclk / 8
147 //     <o9.26..27>  PCLK_CAN1: Peripheral Clock Selection for CAN1
148 //                     <0=> Pclk = Cclk / 4
149 //                     <1=> Pclk = Cclk
150 //                     <2=> Pclk = Cclk / 2
151 //                     <3=> Pclk = Hclk / 6
152 //     <o9.28..29>  PCLK_CAN2: Peripheral Clock Selection for CAN2
153 //                     <0=> Pclk = Cclk / 4
154 //                     <1=> Pclk = Cclk
155 //                     <2=> Pclk = Cclk / 2
156 //                     <3=> Pclk = Hclk / 6
157 //     <o9.30..31>  PCLK_ACF: Peripheral Clock Selection for ACF
158 //                     <0=> Pclk = Cclk / 4
159 //                     <1=> Pclk = Cclk
160 //                     <2=> Pclk = Cclk / 2
161 //                     <3=> Pclk = Hclk / 6
162 //   </h>
163 //
164 //   <h> Peripheral Clock Selection Register 1 (PCLKSEL1)
165 //     <o10.0..1>   PCLK_QEI: Peripheral Clock Selection for the Quadrature Encoder Interface
166 //                     <0=> Pclk = Cclk / 4
167 //                     <1=> Pclk = Cclk
168 //                     <2=> Pclk = Cclk / 2
169 //                     <3=> Pclk = Hclk / 8
170 //     <o10.2..3>   PCLK_GPIO: Peripheral Clock Selection for GPIOs
171 //                     <0=> Pclk = Cclk / 4
172 //                     <1=> Pclk = Cclk
173 //                     <2=> Pclk = Cclk / 2
174 //                     <3=> Pclk = Hclk / 8
175 //     <o10.4..5>   PCLK_PCB: Peripheral Clock Selection for the Pin Connect Block
176 //                     <0=> Pclk = Cclk / 4
177 //                     <1=> Pclk = Cclk
178 //                     <2=> Pclk = Cclk / 2
179 //                     <3=> Pclk = Hclk / 8
180 //     <o10.6..7>   PCLK_I2C1: Peripheral Clock Selection for I2C1
181 //                     <0=> Pclk = Cclk / 4
182 //                     <1=> Pclk = Cclk
183 //                     <2=> Pclk = Cclk / 2
184 //                     <3=> Pclk = Hclk / 8
185 //     <o10.10..11> PCLK_SSP0: Peripheral Clock Selection for SSP0
186 //                     <0=> Pclk = Cclk / 4
187 //                     <1=> Pclk = Cclk
188 //                     <2=> Pclk = Cclk / 2
189 //                     <3=> Pclk = Hclk / 8
190 //     <o10.12..13> PCLK_TIMER2: Peripheral Clock Selection for TIMER2
191 //                     <0=> Pclk = Cclk / 4
192 //                     <1=> Pclk = Cclk
193 //                     <2=> Pclk = Cclk / 2
194 //                     <3=> Pclk = Hclk / 8
195 //     <o10.14..15> PCLK_TIMER3: Peripheral Clock Selection for TIMER3
196 //                     <0=> Pclk = Cclk / 4
197 //                     <1=> Pclk = Cclk
198 //                     <2=> Pclk = Cclk / 2
199 //                     <3=> Pclk = Hclk / 8
200 //     <o10.16..17> PCLK_UART2: Peripheral Clock Selection for UART2
201 //                     <0=> Pclk = Cclk / 4
202 //                     <1=> Pclk = Cclk
203 //                     <2=> Pclk = Cclk / 2
204 //                     <3=> Pclk = Hclk / 8
205 //     <o10.18..19> PCLK_UART3: Peripheral Clock Selection for UART3
206 //                     <0=> Pclk = Cclk / 4
207 //                     <1=> Pclk = Cclk
208 //                     <2=> Pclk = Cclk / 2
209 //                     <3=> Pclk = Hclk / 8
210 //     <o10.20..21> PCLK_I2C2: Peripheral Clock Selection for I2C2
211 //                     <0=> Pclk = Cclk / 4
212 //                     <1=> Pclk = Cclk
213 //                     <2=> Pclk = Cclk / 2
214 //                     <3=> Pclk = Hclk / 8
215 //     <o10.22..23> PCLK_I2S: Peripheral Clock Selection for I2S
216 //                     <0=> Pclk = Cclk / 4
217 //                     <1=> Pclk = Cclk
218 //                     <2=> Pclk = Cclk / 2
219 //                     <3=> Pclk = Hclk / 8
220 //     <o10.26..27> PCLK_RIT: Peripheral Clock Selection for the Repetitive Interrupt Timer
221 //                     <0=> Pclk = Cclk / 4
222 //                     <1=> Pclk = Cclk
223 //                     <2=> Pclk = Cclk / 2
224 //                     <3=> Pclk = Hclk / 8
225 //     <o10.28..29> PCLK_SYSCON: Peripheral Clock Selection for the System Control Block
226 //                     <0=> Pclk = Cclk / 4
227 //                     <1=> Pclk = Cclk
228 //                     <2=> Pclk = Cclk / 2
229 //                     <3=> Pclk = Hclk / 8
230 //     <o10.30..31> PCLK_MC: Peripheral Clock Selection for the Motor Control PWM
231 //                     <0=> Pclk = Cclk / 4
232 //                     <1=> Pclk = Cclk
233 //                     <2=> Pclk = Cclk / 2
234 //                     <3=> Pclk = Hclk / 8
235 //   </h>
236 //
237 //   <h> Power Control for Peripherals Register (PCONP)
238 //     <o11.1>      PCTIM0: Timer/Counter 0 power/clock enable
239 //     <o11.2>      PCTIM1: Timer/Counter 1 power/clock enable
240 //     <o11.3>      PCUART0: UART 0 power/clock enable
241 //     <o11.4>      PCUART1: UART 1 power/clock enable
242 //     <o11.6>      PCPWM1: PWM 1 power/clock enable
243 //     <o11.7>      PCI2C0: I2C interface 0 power/clock enable
244 //     <o11.8>      PCSPI: SPI interface power/clock enable
245 //     <o11.9>      PCRTC: RTC power/clock enable
246 //     <o11.10>     PCSSP1: SSP interface 1 power/clock enable
247 //     <o11.12>     PCAD: A/D converter power/clock enable
248 //     <o11.13>     PCCAN1: CAN controller 1 power/clock enable
249 //     <o11.14>     PCCAN2: CAN controller 2 power/clock enable
250 //     <o11.15>     PCGPIO: GPIOs power/clock enable
251 //     <o11.16>     PCRIT: Repetitive interrupt timer power/clock enable
252 //     <o11.17>     PCMC: Motor control PWM power/clock enable
253 //     <o11.18>     PCQEI: Quadrature encoder interface power/clock enable
254 //     <o11.19>     PCI2C1: I2C interface 1 power/clock enable
255 //     <o11.21>     PCSSP0: SSP interface 0 power/clock enable
256 //     <o11.22>     PCTIM2: Timer 2 power/clock enable
257 //     <o11.23>     PCTIM3: Timer 3 power/clock enable
258 //     <o11.24>     PCUART2: UART 2 power/clock enable
259 //     <o11.25>     PCUART3: UART 3 power/clock enable
260 //     <o11.26>     PCI2C2: I2C interface 2 power/clock enable
261 //     <o11.27>     PCI2S: I2S interface power/clock enable
262 //     <o11.29>     PCGPDMA: GP DMA function power/clock enable
263 //     <o11.30>     PCENET: Ethernet block power/clock enable
264 //     <o11.31>     PCUSB: USB interface power/clock enable
265 //   </h>
266 //
267 //    0x842887DE =
268 //    1000 0100 0010 1000 1000 0111 1101 1110
269 //
270 //   <h> Clock Output Configuration Register (CLKOUTCFG)
271 //     <o12.0..3>   CLKOUTSEL: Selects clock source for CLKOUT
272 //                     <0=> CPU clock
273 //                     <1=> Main oscillator
274 //                     <2=> Internal RC oscillator
275 //                     <3=> USB clock
276 //                     <4=> RTC oscillator
277 //     <o12.4..7>   CLKOUTDIV: Selects clock divider for CLKOUT
278 //                     <1-16><#-1>
279 //     <o12.8>      CLKOUT_EN: CLKOUT enable control
280 //   </h>
281 //
282 // </e>
283 */
284 #define CLOCK_SETUP           1
285 #define SCS_Val               0x00000020
286 #define CLKSRCSEL_Val         0x00000001
287 #define PLL0_SETUP            1
288 #define PLL0CFG_Val           0x0000000B
289 #define PLL1_SETUP            1
290 #define PLL1CFG_Val           0x00000023
291 #define CCLKCFG_Val           0x00000003
292 #define USBCLKCFG_Val         0x00000000
293 #define PCLKSEL0_Val          0x00000000
294 #define PCLKSEL1_Val          0x00000000
295 #define PCONP_Val             0x842887DE
296 #define CLKOUTCFG_Val         0x00000000
297
298
299 /*--------------------- Flash Accelerator Configuration ----------------------
300 //
301 // <e> Flash Accelerator Configuration
302 //   <o1.0..1>   FETCHCFG: Fetch Configuration
303 //               <0=> Instruction fetches from flash are not buffered
304 //               <1=> One buffer is used for all instruction fetch buffering
305 //               <2=> All buffers may be used for instruction fetch buffering
306 //               <3=> Reserved (do not use this setting)
307 //   <o1.2..3>   DATACFG: Data Configuration
308 //               <0=> Data accesses from flash are not buffered
309 //               <1=> One buffer is used for all data access buffering
310 //               <2=> All buffers may be used for data access buffering
311 //               <3=> Reserved (do not use this setting)
312 //   <o1.4>      ACCEL: Acceleration Enable
313 //   <o1.5>      PREFEN: Prefetch Enable
314 //   <o1.6>      PREFOVR: Prefetch Override
315 //   <o1.12..15> FLASHTIM: Flash Access Time
316 //               <0=> 1 CPU clock (for CPU clock up to 20 MHz)
317 //               <1=> 2 CPU clocks (for CPU clock up to 40 MHz)
318 //               <2=> 3 CPU clocks (for CPU clock up to 60 MHz)
319 //               <3=> 4 CPU clocks (for CPU clock up to 80 MHz)
320 //               <4=> 5 CPU clocks (for CPU clock up to 100 MHz)
321 //               <5=> 6 CPU clocks (for any CPU clock)
322 // </e>
323 */
324 #define FLASH_SETUP           1
325 #define FLASHCFG_Val          0x0000303A
326
327 /*
328 //-------- <<< end of configuration section >>> ------------------------------
329 */
330
331 /*----------------------------------------------------------------------------
332   Check the register settings
333  *----------------------------------------------------------------------------*/
334 #define CHECK_RANGE(val, min, max)                ((val < min) || (val > max))
335 #define CHECK_RSVD(val, mask)                     (val & mask)
336
337 /* Clock Configuration -------------------------------------------------------*/
338 #if (CHECK_RSVD((SCS_Val),       ~0x00000030))
339    #error "SCS: Invalid values of reserved bits!"
340 #endif
341
342 #if (CHECK_RANGE((CLKSRCSEL_Val), 0, 2))
343    #error "CLKSRCSEL: Value out of range!"
344 #endif
345
346 #if (CHECK_RSVD((PLL0CFG_Val),   ~0x00FF7FFF))
347    #error "PLL0CFG: Invalid values of reserved bits!"
348 #endif
349
350 #if (CHECK_RSVD((PLL1CFG_Val),   ~0x0000007F))
351    #error "PLL1CFG: Invalid values of reserved bits!"
352 #endif
353
354 #if ((CCLKCFG_Val != 0) && (((CCLKCFG_Val - 1) % 2)))
355    #error "CCLKCFG: CCLKSEL field does not contain only odd values or 0!"
356 #endif
357
358 #if (CHECK_RSVD((USBCLKCFG_Val), ~0x0000000F))
359    #error "USBCLKCFG: Invalid values of reserved bits!"
360 #endif
361
362 #if (CHECK_RSVD((PCLKSEL0_Val),   0x000C0C00))
363    #error "PCLKSEL0: Invalid values of reserved bits!"
364 #endif
365
366 #if (CHECK_RSVD((PCLKSEL1_Val),   0x03000300))
367    #error "PCLKSEL1: Invalid values of reserved bits!"
368 #endif
369
370 #if (CHECK_RSVD((PCONP_Val),      0x10100821))
371    #error "PCONP: Invalid values of reserved bits!"
372 #endif
373
374 #if (CHECK_RSVD((CLKOUTCFG_Val), ~0x000001FF))
375    #error "CLKOUTCFG: Invalid values of reserved bits!"
376 #endif
377
378 /* Flash Accelerator Configuration -------------------------------------------*/
379 #if (CHECK_RSVD((FLASHCFG_Val), ~0x0000F07F))
380    #error "FLASHCFG: Invalid values of reserved bits!"
381 #endif
382
383
384 /*----------------------------------------------------------------------------
385   DEFINES
386  *----------------------------------------------------------------------------*/
387
388 /*----------------------------------------------------------------------------
389   Define clocks
390  *----------------------------------------------------------------------------*/
391 #define XTAL        (12000000UL)        /* Oscillator frequency               */
392 #define OSC_CLK     (      XTAL)        /* Main oscillator frequency          */
393 #define RTC_CLK     (   32000UL)        /* RTC oscillator frequency           */
394 #define IRC_OSC     ( 4000000UL)        /* Internal RC oscillator frequency   */
395
396
397 /*----------------------------------------------------------------------------
398   Clock Variable definitions
399  *----------------------------------------------------------------------------*/
400 uint32_t SystemFrequency = IRC_OSC; /*!< System Clock Frequency (Core Clock)  */
401
402
403 /**
404  * Initialize the system
405  *
406  * @param  none
407  * @return none
408  *
409  * @brief  Setup the microcontroller system.
410  *         Initialize the System and update the SystemFrequency variable.
411  */
412 void SystemInit (void)
413 {
414 #if (CLOCK_SETUP)                       /* Clock Setup                        */
415   SC->SCS       = SCS_Val;
416   if (SCS_Val & (1 << 5)) {             /* If Main Oscillator is enabled      */
417     while ((SC->SCS & (1 << 6)) == 0);  /* Wait for Oscillator to be ready    */
418   }
419
420   SC->CCLKCFG   = CCLKCFG_Val;          /* Setup Clock Divider                */
421
422 #if (PLL0_SETUP)
423   SC->CLKSRCSEL = CLKSRCSEL_Val;        /* Select Clock Source for PLL0       */
424   SC->PLL0CFG   = PLL0CFG_Val;
425   SC->PLL0CON   = 0x01;                 /* PLL0 Enable                        */
426   SC->PLL0FEED  = 0xAA;
427   SC->PLL0FEED  = 0x55;
428   while (!(SC->PLL0STAT & (1 << 26)));  /* Wait for PLOCK0                    */
429
430   SC->PLL0CON   = 0x03;                 /* PLL0 Enable & Connect              */
431   SC->PLL0FEED  = 0xAA;
432   SC->PLL0FEED  = 0x55;
433 #endif
434
435 #if (PLL1_SETUP)
436   SC->PLL1CFG   = PLL1CFG_Val;
437   SC->PLL1CON   = 0x01;                 /* PLL1 Enable                        */
438   SC->PLL1FEED  = 0xAA;
439   SC->PLL1FEED  = 0x55;
440   while (!(SC->PLL1STAT & (1 << 10)));  /* Wait for PLOCK1                    */
441
442   SC->PLL1CON   = 0x03;                 /* PLL1 Enable & Connect              */
443   SC->PLL1FEED  = 0xAA;
444   SC->PLL1FEED  = 0x55;
445 #else
446   SC->USBCLKCFG = USBCLKCFG_Val;        /* Setup USB Clock Divider            */
447 #endif
448
449   SC->PCLKSEL0  = PCLKSEL0_Val;         /* Peripheral Clock Selection         */
450   SC->PCLKSEL1  = PCLKSEL1_Val;
451
452   SC->PCONP     = PCONP_Val;            /* Power Control for Peripherals      */
453
454   SC->CLKOUTCFG = CLKOUTCFG_Val;        /* Clock Output Configuration         */
455 #endif
456
457   /* Determine clock frequency according to clock register values             */
458   if (((SC->PLL0STAT >> 24) & 3) == 3) {/* If PLL0 enabled and connected      */
459     switch (SC->CLKSRCSEL & 0x03) {
460       case 0:                           /* Internal RC oscillator => PLL0     */
461       case 3:                           /* Reserved, default to Internal RC   */
462         SystemFrequency = (IRC_OSC *
463                           (((2 * ((SC->PLL0STAT & 0x7FFF) + 1))) /
464                           (((SC->PLL0STAT >> 16) & 0xFF) + 1))   /
465                           ((SC->CCLKCFG & 0xFF)+ 1));
466         break;
467       case 1:                           /* Main oscillator => PLL0            */
468         SystemFrequency = (OSC_CLK *
469                           (((2 * ((SC->PLL0STAT & 0x7FFF) + 1))) /
470                           (((SC->PLL0STAT >> 16) & 0xFF) + 1))   /
471                           ((SC->CCLKCFG & 0xFF)+ 1));
472         break;
473       case 2:                           /* RTC oscillator => PLL0             */
474         SystemFrequency = (RTC_CLK *
475                           (((2 * ((SC->PLL0STAT & 0x7FFF) + 1))) /
476                           (((SC->PLL0STAT >> 16) & 0xFF) + 1))   /
477                           ((SC->CCLKCFG & 0xFF)+ 1));
478         break;
479     }
480   } else {
481     switch (SC->CLKSRCSEL & 0x03) {
482       case 0:                           /* Internal RC oscillator => PLL0     */
483       case 3:                           /* Reserved, default to Internal RC   */
484         SystemFrequency = IRC_OSC / ((SC->CCLKCFG & 0xFF)+ 1);
485         break;
486       case 1:                           /* Main oscillator => PLL0            */
487         SystemFrequency = OSC_CLK / ((SC->CCLKCFG & 0xFF)+ 1);
488         break;
489       case 2:                           /* RTC oscillator => PLL0             */
490         SystemFrequency = RTC_CLK / ((SC->CCLKCFG & 0xFF)+ 1);
491         break;
492     }
493   }
494
495 #if (FLASH_SETUP == 1)                  /* Flash Accelerator Setup            */
496   SC->FLASHCFG  = FLASHCFG_Val;
497 #endif
498 }