1 /******************************************************************************
3 * @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
4 * NXP LPC17xx Device Series
7 *----------------------------------------------------------------------------
9 * Copyright (C) 2008 ARM Limited. All rights reserved.
11 * ARM Limited (ARM) is supplying this software for use with Cortex-M3
12 * processor based microcontrollers. This file can be freely distributed
13 * within development tools that are supporting such ARM based processors.
15 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
16 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
18 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
19 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
21 ******************************************************************************/
28 * ==========================================================================
29 * ---------- Interrupt Number Definition -----------------------------------
30 * ==========================================================================
35 /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
36 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
37 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
38 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
39 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
40 SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
41 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
42 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
43 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
45 /****** LPC17xx Specific Interrupt Numbers *******************************************************/
46 WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
47 TIMER0_IRQn = 1, /*!< Timer0 Interrupt */
48 TIMER1_IRQn = 2, /*!< Timer1 Interrupt */
49 TIMER2_IRQn = 3, /*!< Timer2 Interrupt */
50 TIMER3_IRQn = 4, /*!< Timer3 Interrupt */
51 UART0_IRQn = 5, /*!< UART0 Interrupt */
52 UART1_IRQn = 6, /*!< UART1 Interrupt */
53 UART2_IRQn = 7, /*!< UART2 Interrupt */
54 UART3_IRQn = 8, /*!< UART3 Interrupt */
55 PWM1_IRQn = 9, /*!< PWM1 Interrupt */
56 I2C0_IRQn = 10, /*!< I2C0 Interrupt */
57 I2C1_IRQn = 11, /*!< I2C1 Interrupt */
58 I2C2_IRQn = 12, /*!< I2C2 Interrupt */
59 SPI_IRQn = 13, /*!< SPI Interrupt */
60 SSP0_IRQn = 14, /*!< SSP0 Interrupt */
61 SSP1_IRQn = 15, /*!< SSP1 Interrupt */
62 PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */
63 RTC_IRQn = 17, /*!< Real Time Clock Interrupt */
64 EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */
65 EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */
66 EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */
67 EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */
68 ADC_IRQn = 22, /*!< A/D Converter Interrupt */
69 BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */
70 USB_IRQn = 24, /*!< USB Interrupt */
71 CAN_IRQn = 25, /*!< CAN Interrupt */
72 DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */
73 I2S_IRQn = 27, /*!< I2S Interrupt */
74 ENET_IRQn = 28, /*!< Ethernet Interrupt */
75 RIT_IRQn = 29, /*!< Repetitive Interrupt Timer Interrupt */
76 MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */
77 QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */
78 PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */
83 * ==========================================================================
84 * ----------- Processor and Core Peripheral Section ------------------------
85 * ==========================================================================
88 /* Configuration of the Cortex-M3 Processor and Core Peripherals */
89 #define __MPU_PRESENT 1 /*!< MPU present or not */
90 #define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */
91 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
94 #include "../cortex_m3/core_cm3.h" /* Cortex-M3 processor and core peripherals */
95 #include "system.h" /* System Header */
100 * Initialize the system clock
105 * @brief Setup the microcontroller system.
106 * Initialize the System and update the SystemFrequency variable.
108 extern void SystemInit (void);
111 /******************************************************************************/
112 /* Device Specific Peripheral registers structures */
113 /******************************************************************************/
117 /*------------- System Control (SC) ------------------------------------------*/
120 __IO uint32_t FLASHCFG; /* Flash Accelerator Module */
121 uint32_t RESERVED0[31];
122 __IO uint32_t PLL0CON; /* Clocking and Power Control */
123 __IO uint32_t PLL0CFG;
124 __I uint32_t PLL0STAT;
125 __O uint32_t PLL0FEED;
126 uint32_t RESERVED1[4];
127 __IO uint32_t PLL1CON;
128 __IO uint32_t PLL1CFG;
129 __I uint32_t PLL1STAT;
130 __O uint32_t PLL1FEED;
131 uint32_t RESERVED2[4];
134 uint32_t RESERVED3[15];
135 __IO uint32_t CCLKCFG;
136 __IO uint32_t USBCLKCFG;
137 __IO uint32_t CLKSRCSEL;
138 uint32_t RESERVED4[12];
139 __IO uint32_t EXTINT; /* External Interrupts */
141 __IO uint32_t EXTMODE;
142 __IO uint32_t EXTPOLAR;
143 uint32_t RESERVED6[12];
144 __IO uint32_t RSID; /* Reset */
145 uint32_t RESERVED7[7];
146 __IO uint32_t SCS; /* Syscon Miscellaneous Registers */
147 __IO uint32_t IRCTRIM; /* Clock Dividers */
148 __IO uint32_t PCLKSEL0;
149 __IO uint32_t PCLKSEL1;
150 uint32_t RESERVED8[4];
151 __IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */
153 __IO uint32_t CLKOUTCFG; /* Clock Output Configuration */
156 /*------------- Pin Connect Block (PINCON) -----------------------------------*/
159 __IO uint32_t PINSEL0;
160 __IO uint32_t PINSEL1;
161 __IO uint32_t PINSEL2;
162 __IO uint32_t PINSEL3;
163 __IO uint32_t PINSEL4;
164 __IO uint32_t PINSEL5;
165 __IO uint32_t PINSEL6;
166 __IO uint32_t PINSEL7;
167 __IO uint32_t PINSEL8;
168 __IO uint32_t PINSEL9;
169 __IO uint32_t PINSEL10;
170 uint32_t RESERVED0[5];
171 __IO uint32_t PINMODE0;
172 __IO uint32_t PINMODE1;
173 __IO uint32_t PINMODE2;
174 __IO uint32_t PINMODE3;
175 __IO uint32_t PINMODE4;
176 __IO uint32_t PINMODE5;
177 __IO uint32_t PINMODE6;
178 __IO uint32_t PINMODE7;
179 __IO uint32_t PINMODE8;
180 __IO uint32_t PINMODE9;
181 __IO uint32_t PINMODE_OD0;
182 __IO uint32_t PINMODE_OD1;
183 __IO uint32_t PINMODE_OD2;
184 __IO uint32_t PINMODE_OD3;
185 __IO uint32_t PINMODE_OD4;
188 /*------------- General Purpose Input/Output (GPIO) --------------------------*/
191 __IO uint32_t FIODIR;
192 uint32_t RESERVED0[3];
193 __IO uint32_t FIOMASK;
194 __IO uint32_t FIOPIN;
195 __IO uint32_t FIOSET;
201 __I uint32_t IntStatus;
202 __I uint32_t IO0IntStatR;
203 __I uint32_t IO0IntStatF;
204 __O uint32_t IO0IntClr;
205 __IO uint32_t IO0IntEnR;
206 __IO uint32_t IO0IntEnF;
207 uint32_t RESERVED0[3];
208 __I uint32_t IO2IntStatR;
209 __I uint32_t IO2IntStatF;
210 __O uint32_t IO2IntClr;
211 __IO uint32_t IO2IntEnR;
212 __IO uint32_t IO2IntEnF;
215 /*------------- Timer (TIM) --------------------------------------------------*/
231 uint32_t RESERVED0[2];
233 uint32_t RESERVED1[24];
237 /*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
260 uint32_t RESERVED0[7];
264 /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
282 uint8_t RESERVED1[7];
284 uint8_t RESERVED2[7];
286 uint8_t RESERVED3[3];
289 uint8_t RESERVED4[3];
291 uint8_t RESERVED5[7];
293 uint8_t RESERVED6[27];
294 __IO uint8_t RS485CTRL;
295 uint8_t RESERVED7[3];
296 __IO uint8_t ADRMATCH;
316 uint8_t RESERVED1[3];
318 uint8_t RESERVED2[3];
320 uint8_t RESERVED3[3];
322 uint8_t RESERVED4[3];
324 uint8_t RESERVED5[3];
330 uint8_t RESERVED8[27];
331 __IO uint8_t RS485CTRL;
332 uint8_t RESERVED9[3];
333 __IO uint8_t ADRMATCH;
334 uint8_t RESERVED10[3];
335 __IO uint8_t RS485DLY;
338 /*------------- Serial Peripheral Interface (SPI) ----------------------------*/
345 uint32_t RESERVED0[3];
349 /*------------- Synchronous Serial Communication (SSP) -----------------------*/
364 /*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
367 __IO uint32_t I2CONSET;
370 __IO uint32_t I2ADR0;
371 __IO uint32_t I2SCLH;
372 __IO uint32_t I2SCLL;
373 __O uint32_t I2CONCLR;
374 __IO uint32_t MMCTRL;
375 __IO uint32_t I2ADR1;
376 __IO uint32_t I2ADR2;
377 __IO uint32_t I2ADR3;
378 __I uint32_t I2DATA_BUFFER;
379 __IO uint32_t I2MASK0;
380 __IO uint32_t I2MASK1;
381 __IO uint32_t I2MASK2;
382 __IO uint32_t I2MASK3;
385 /*------------- Inter IC Sound (I2S) -----------------------------------------*/
388 __IO uint32_t I2SDAO;
390 __O uint32_t I2STXFIFO;
391 __I uint32_t I2SRXFIFO;
392 __I uint32_t I2SSTATE;
393 __IO uint32_t I2SDMA1;
394 __IO uint32_t I2SDMA2;
395 __IO uint32_t I2SIRQ;
396 __IO uint32_t I2STXRATE;
397 __IO uint32_t I2SRXRATE;
398 __IO uint32_t I2STXBITRATE;
399 __IO uint32_t I2SRXBITRATE;
400 __IO uint32_t I2STXMODE;
401 __IO uint32_t I2SRXMODE;
404 /*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/
407 __IO uint32_t RICOMPVAL;
408 __IO uint32_t RIMASK;
410 uint8_t RESERVED0[3];
411 __IO uint32_t RICOUNTER;
414 /*------------- Real-Time Clock (RTC) ----------------------------------------*/
418 uint8_t RESERVED0[3];
420 uint8_t RESERVED1[3];
422 uint8_t RESERVED2[3];
424 uint8_t RESERVED3[3];
429 uint8_t RESERVED4[3];
431 uint8_t RESERVED5[3];
433 uint8_t RESERVED6[3];
435 uint8_t RESERVED7[3];
437 uint8_t RESERVED8[3];
441 uint8_t RESERVED10[3];
444 __IO uint32_t CALIBRATION;
445 __IO uint32_t GPREG0;
446 __IO uint32_t GPREG1;
447 __IO uint32_t GPREG2;
448 __IO uint32_t GPREG3;
449 __IO uint32_t GPREG4;
450 __IO uint8_t WAKEUPDIS;
451 uint8_t RESERVED12[3];
452 __IO uint8_t PWRCTRL;
453 uint8_t RESERVED13[3];
455 uint8_t RESERVED14[3];
457 uint8_t RESERVED15[3];
459 uint8_t RESERVED16[3];
461 uint8_t RESERVED17[3];
463 uint8_t RESERVED18[3];
467 uint8_t RESERVED20[3];
468 __IO uint16_t ALYEAR;
472 /*------------- Watchdog Timer (WDT) -----------------------------------------*/
476 uint8_t RESERVED0[3];
479 uint8_t RESERVED1[3];
481 __IO uint32_t WDCLKSEL;
484 /*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
490 __IO uint32_t ADINTEN;
503 /*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
507 __IO uint32_t DACCTRL;
508 __IO uint16_t DACCNTVAL;
511 /*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/
515 __O uint32_t MCCON_SET;
516 __O uint32_t MCCON_CLR;
517 __I uint32_t MCCAPCON;
518 __O uint32_t MCCAPCON_SET;
519 __O uint32_t MCCAPCON_CLR;
520 __IO uint32_t MCTIM0;
521 __IO uint32_t MCTIM1;
522 __IO uint32_t MCTIM2;
523 __IO uint32_t MCPER0;
524 __IO uint32_t MCPER1;
525 __IO uint32_t MCPER2;
529 __IO uint32_t MCDEADTIME;
534 __I uint32_t MCINTEN;
535 __O uint32_t MCINTEN_SET;
536 __O uint32_t MCINTEN_CLR;
537 __I uint32_t MCCNTCON;
538 __O uint32_t MCCNTCON_SET;
539 __O uint32_t MCCNTCON_CLR;
540 __I uint32_t MCINTFLAG;
541 __O uint32_t MCINTFLAG_SET;
542 __O uint32_t MCINTFLAG_CLR;
543 __O uint32_t MCCAP_CLR;
546 /*------------- Quadrature Encoder Interface (QEI) ---------------------------*/
550 __I uint32_t QEISTAT;
551 __IO uint32_t QEICONF;
553 __IO uint32_t QEIMAXPOS;
554 __IO uint32_t CMPOS0;
555 __IO uint32_t CMPOS1;
556 __IO uint32_t CMPOS2;
558 __IO uint32_t INXCMP;
559 __IO uint32_t QEILOAD;
560 __I uint32_t QEITIME;
563 __IO uint32_t VELCOMP;
564 __IO uint32_t FILTER;
565 uint32_t RESERVED0[998];
568 __I uint32_t QEIINTSTAT;
574 /*------------- Controller Area Network (CAN) --------------------------------*/
577 __IO uint32_t mask[512]; /* ID Masks */
580 typedef struct /* Acceptance Filter Registers */
583 __IO uint32_t SFF_sa;
584 __IO uint32_t SFF_GRP_sa;
585 __IO uint32_t EFF_sa;
586 __IO uint32_t EFF_GRP_sa;
587 __IO uint32_t ENDofTable;
588 __I uint32_t LUTerrAd;
592 typedef struct /* Central Registers */
594 __I uint32_t CANTxSR;
595 __I uint32_t CANRxSR;
599 typedef struct /* Controller Registers */
627 /*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
628 typedef struct /* Common Registers */
630 __I uint32_t DMACIntStat;
631 __I uint32_t DMACIntTCStat;
632 __O uint32_t DMACIntTCClear;
633 __I uint32_t DMACIntErrStat;
634 __O uint32_t DMACIntErrClr;
635 __I uint32_t DMACRawIntTCStat;
636 __I uint32_t DMACRawIntErrStat;
637 __I uint32_t DMACEnbldChns;
638 __IO uint32_t DMACSoftBReq;
639 __IO uint32_t DMACSoftSReq;
640 __IO uint32_t DMACSoftLBReq;
641 __IO uint32_t DMACSoftLSReq;
642 __IO uint32_t DMACConfig;
643 __IO uint32_t DMACSync;
646 typedef struct /* Channel Registers */
648 __IO uint32_t DMACCSrcAddr;
649 __IO uint32_t DMACCDestAddr;
650 __IO uint32_t DMACCLLI;
651 __IO uint32_t DMACCControl;
652 __IO uint32_t DMACCConfig;
655 /*------------- Universal Serial Bus (USB) -----------------------------------*/
658 __I uint32_t HcRevision; /* USB Host Registers */
659 __IO uint32_t HcControl;
660 __IO uint32_t HcCommandStatus;
661 __IO uint32_t HcInterruptStatus;
662 __IO uint32_t HcInterruptEnable;
663 __IO uint32_t HcInterruptDisable;
664 __IO uint32_t HcHCCA;
665 __I uint32_t HcPeriodCurrentED;
666 __IO uint32_t HcControlHeadED;
667 __IO uint32_t HcControlCurrentED;
668 __IO uint32_t HcBulkHeadED;
669 __IO uint32_t HcBulkCurrentED;
670 __I uint32_t HcDoneHead;
671 __IO uint32_t HcFmInterval;
672 __I uint32_t HcFmRemaining;
673 __I uint32_t HcFmNumber;
674 __IO uint32_t HcPeriodicStart;
675 __IO uint32_t HcLSTreshold;
676 __IO uint32_t HcRhDescriptorA;
677 __IO uint32_t HcRhDescriptorB;
678 __IO uint32_t HcRhStatus;
679 __IO uint32_t HcRhPortStatus1;
680 __IO uint32_t HcRhPortStatus2;
681 uint32_t RESERVED0[40];
682 __I uint32_t Module_ID;
684 __I uint32_t OTGIntSt; /* USB On-The-Go Registers */
685 __IO uint32_t OTGIntEn;
686 __O uint32_t OTGIntSet;
687 __O uint32_t OTGIntClr;
688 __IO uint32_t OTGStCtrl;
689 __IO uint32_t OTGTmr;
690 uint32_t RESERVED1[58];
692 __I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */
693 __IO uint32_t USBDevIntEn;
694 __O uint32_t USBDevIntClr;
695 __O uint32_t USBDevIntSet;
697 __O uint32_t USBCmdCode; /* USB Device SIE Command Registers */
698 __I uint32_t USBCmdData;
700 __I uint32_t USBRxData; /* USB Device Transfer Registers */
701 __O uint32_t USBTxData;
702 __I uint32_t USBRxPLen;
703 __O uint32_t USBTxPLen;
704 __IO uint32_t USBCtrl;
705 __O uint32_t USBDevIntPri;
707 __I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */
708 __IO uint32_t USBEpIntEn;
709 __O uint32_t USBEpIntClr;
710 __O uint32_t USBEpIntSet;
711 __O uint32_t USBEpIntPri;
713 __IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/
714 __O uint32_t USBEpInd;
715 __IO uint32_t USBMaxPSize;
717 __I uint32_t USBDMARSt; /* USB Device DMA Registers */
718 __O uint32_t USBDMARClr;
719 __O uint32_t USBDMARSet;
720 uint32_t RESERVED2[9];
721 __IO uint32_t USBUDCAH;
722 __I uint32_t USBEpDMASt;
723 __O uint32_t USBEpDMAEn;
724 __O uint32_t USBEpDMADis;
725 __I uint32_t USBDMAIntSt;
726 __IO uint32_t USBDMAIntEn;
727 uint32_t RESERVED3[2];
728 __I uint32_t USBEoTIntSt;
729 __O uint32_t USBEoTIntClr;
730 __O uint32_t USBEoTIntSet;
731 __I uint32_t USBNDDRIntSt;
732 __O uint32_t USBNDDRIntClr;
733 __O uint32_t USBNDDRIntSet;
734 __I uint32_t USBSysErrIntSt;
735 __O uint32_t USBSysErrIntClr;
736 __O uint32_t USBSysErrIntSet;
737 uint32_t RESERVED4[15];
739 __I uint32_t I2C_RX; /* USB OTG I2C Registers */
741 __I uint32_t I2C_STS;
742 __IO uint32_t I2C_CTL;
743 __IO uint32_t I2C_CLKHI;
744 __O uint32_t I2C_CLKLO;
745 uint32_t RESERVED5[823];
748 __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */
749 __IO uint32_t OTGClkCtrl;
752 __I uint32_t USBClkSt;
753 __I uint32_t OTGClkSt;
757 /*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
760 __IO uint32_t MAC1; /* MAC Registers */
774 uint32_t RESERVED0[2];
778 uint32_t RESERVED1[45];
779 __IO uint32_t Command; /* Control Registers */
781 __IO uint32_t RxDescriptor;
782 __IO uint32_t RxStatus;
783 __IO uint32_t RxDescriptorNumber;
784 __I uint32_t RxProduceIndex;
785 __IO uint32_t RxConsumeIndex;
786 __IO uint32_t TxDescriptor;
787 __IO uint32_t TxStatus;
788 __IO uint32_t TxDescriptorNumber;
789 __IO uint32_t TxProduceIndex;
790 __I uint32_t TxConsumeIndex;
791 uint32_t RESERVED2[10];
795 uint32_t RESERVED3[3];
796 __IO uint32_t FlowControlCounter;
797 __I uint32_t FlowControlStatus;
798 uint32_t RESERVED4[34];
799 __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */
800 __IO uint32_t RxFilterWoLStatus;
801 __IO uint32_t RxFilterWoLClear;
803 __IO uint32_t HashFilterL;
804 __IO uint32_t HashFilterH;
805 uint32_t RESERVED6[882];
806 __I uint32_t IntStatus; /* Module Control Registers */
807 __IO uint32_t IntEnable;
808 __O uint32_t IntClear;
811 __IO uint32_t PowerDown;
813 __IO uint32_t Module_ID;
816 #pragma no_anon_unions
819 /******************************************************************************/
820 /* Peripheral memory map */
821 /******************************************************************************/
823 #define FLASH_BASE (0x00000000UL)
824 #define RAM_BASE (0x10000000UL)
825 #define GPIO_BASE (0x2009C000UL)
826 #define APB0_BASE (0x40000000UL)
827 #define APB1_BASE (0x40080000UL)
828 #define AHB_BASE (0x50000000UL)
829 #define CM3_BASE (0xE0000000UL)
831 /* APB0 peripherals */
832 #define WDT_BASE (APB0_BASE + 0x00000)
833 #define TIM0_BASE (APB0_BASE + 0x04000)
834 #define TIM1_BASE (APB0_BASE + 0x08000)
835 #define UART0_BASE (APB0_BASE + 0x0C000)
836 #define UART1_BASE (APB0_BASE + 0x10000)
837 #define PWM1_BASE (APB0_BASE + 0x18000)
838 #define I2C0_BASE (APB0_BASE + 0x1C000)
839 #define SPI_BASE (APB0_BASE + 0x20000)
840 #define RTC_BASE (APB0_BASE + 0x24000)
841 #define GPIOINT_BASE (APB0_BASE + 0x28080)
842 #define PINCON_BASE (APB0_BASE + 0x2C000)
843 #define SSP1_BASE (APB0_BASE + 0x30000)
844 #define ADC_BASE (APB0_BASE + 0x34000)
845 #define CANAF_RAM_BASE (APB0_BASE + 0x38000)
846 #define CANAF_BASE (APB0_BASE + 0x3C000)
847 #define CANCR_BASE (APB0_BASE + 0x40000)
848 #define CAN1_BASE (APB0_BASE + 0x44000)
849 #define CAN2_BASE (APB0_BASE + 0x48000)
850 #define I2C1_BASE (APB0_BASE + 0x5C000)
852 /* APB1 peripherals */
853 #define SSP0_BASE (APB1_BASE + 0x08000)
854 #define DAC_BASE (APB1_BASE + 0x0C000)
855 #define TIM2_BASE (APB1_BASE + 0x10000)
856 #define TIM3_BASE (APB1_BASE + 0x14000)
857 #define UART2_BASE (APB1_BASE + 0x18000)
858 #define UART3_BASE (APB1_BASE + 0x1C000)
859 #define I2C2_BASE (APB1_BASE + 0x20000)
860 #define I2S_BASE (APB1_BASE + 0x28000)
861 #define RIT_BASE (APB1_BASE + 0x30000)
862 #define MCPWM_BASE (APB1_BASE + 0x38000)
863 #define QEI_BASE (APB1_BASE + 0x3C000)
864 #define SC_BASE (APB1_BASE + 0x7C000)
866 /* AHB peripherals */
867 #define EMAC_BASE (AHB_BASE + 0x00000)
868 #define GPDMA_BASE (AHB_BASE + 0x04000)
869 #define GPDMACH0_BASE (AHB_BASE + 0x04100)
870 #define GPDMACH1_BASE (AHB_BASE + 0x04120)
871 #define GPDMACH2_BASE (AHB_BASE + 0x04140)
872 #define GPDMACH3_BASE (AHB_BASE + 0x04160)
873 #define GPDMACH4_BASE (AHB_BASE + 0x04180)
874 #define GPDMACH5_BASE (AHB_BASE + 0x041A0)
875 #define GPDMACH6_BASE (AHB_BASE + 0x041C0)
876 #define GPDMACH7_BASE (AHB_BASE + 0x041E0)
877 #define USB_BASE (AHB_BASE + 0x0C000)
880 #define GPIO0_BASE (GPIO_BASE + 0x00000)
881 #define GPIO1_BASE (GPIO_BASE + 0x00020)
882 #define GPIO2_BASE (GPIO_BASE + 0x00040)
883 #define GPIO3_BASE (GPIO_BASE + 0x00060)
884 #define GPIO4_BASE (GPIO_BASE + 0x00080)
887 /******************************************************************************/
888 /* Peripheral declaration */
889 /******************************************************************************/
890 #define SC (( SC_TypeDef *) SC_BASE)
891 #define GPIO0 (( GPIO_TypeDef *) GPIO0_BASE)
892 #define GPIO1 (( GPIO_TypeDef *) GPIO1_BASE)
893 #define GPIO2 (( GPIO_TypeDef *) GPIO2_BASE)
894 #define GPIO3 (( GPIO_TypeDef *) GPIO3_BASE)
895 #define GPIO4 (( GPIO_TypeDef *) GPIO4_BASE)
896 #define WDT (( WDT_TypeDef *) WDT_BASE)
897 #define TIM0 (( TIM_TypeDef *) TIM0_BASE)
898 #define TIM1 (( TIM_TypeDef *) TIM1_BASE)
899 #define TIM2 (( TIM_TypeDef *) TIM2_BASE)
900 #define TIM3 (( TIM_TypeDef *) TIM3_BASE)
901 #define RIT (( RIT_TypeDef *) RIT_BASE)
902 #define UART0 (( UART_TypeDef *) UART0_BASE)
903 #define UART1 (( UART1_TypeDef *) UART1_BASE)
904 #define UART2 (( UART_TypeDef *) UART2_BASE)
905 #define UART3 (( UART_TypeDef *) UART3_BASE)
906 #define PWM1 (( PWM_TypeDef *) PWM1_BASE)
907 #define I2C0 (( I2C_TypeDef *) I2C0_BASE)
908 #define I2C1 (( I2C_TypeDef *) I2C1_BASE)
909 #define I2C2 (( I2C_TypeDef *) I2C2_BASE)
910 #define I2S (( I2S_TypeDef *) I2S_BASE)
911 #define SPI (( SPI_TypeDef *) SPI_BASE)
912 #define RTC (( RTC_TypeDef *) RTC_BASE)
913 #define GPIOINT (( GPIOINT_TypeDef *) GPIOINT_BASE)
914 #define PINCON (( PINCON_TypeDef *) PINCON_BASE)
915 #define SSP0 (( SSP_TypeDef *) SSP0_BASE)
916 #define SSP1 (( SSP_TypeDef *) SSP1_BASE)
917 #define ADC (( ADC_TypeDef *) ADC_BASE)
918 #define DAC (( DAC_TypeDef *) DAC_BASE)
919 #define CANAF_RAM ((CANAF_RAM_TypeDef *) CANAF_RAM_BASE)
920 #define CANAF (( CANAF_TypeDef *) CANAF_BASE)
921 #define CANCR (( CANCR_TypeDef *) CANCR_BASE)
922 #define CAN1 (( CAN_TypeDef *) CAN1_BASE)
923 #define CAN2 (( CAN_TypeDef *) CAN2_BASE)
924 #define MCPWM (( MCPWM_TypeDef *) MCPWM_BASE)
925 #define QEI (( QEI_TypeDef *) QEI_BASE)
926 #define EMAC (( EMAC_TypeDef *) EMAC_BASE)
927 #define GPDMA (( GPDMA_TypeDef *) GPDMA_BASE)
928 #define GPDMACH0 (( GPDMACH_TypeDef *) GPDMACH0_BASE)
929 #define GPDMACH1 (( GPDMACH_TypeDef *) GPDMACH1_BASE)
930 #define GPDMACH2 (( GPDMACH_TypeDef *) GPDMACH2_BASE)
931 #define GPDMACH3 (( GPDMACH_TypeDef *) GPDMACH3_BASE)
932 #define GPDMACH4 (( GPDMACH_TypeDef *) GPDMACH4_BASE)
933 #define GPDMACH5 (( GPDMACH_TypeDef *) GPDMACH5_BASE)
934 #define GPDMACH6 (( GPDMACH_TypeDef *) GPDMACH6_BASE)
935 #define GPDMACH7 (( GPDMACH_TypeDef *) GPDMACH7_BASE)
936 #define USB (( USB_TypeDef *) USB_BASE)
938 #endif // __LPC17xx_H__