1 /*----------------------------------------------------------------------------
3 *----------------------------------------------------------------------------
5 * Purpose: USB Hardware Layer Definitions for NXP LPC Family MCUs
7 *----------------------------------------------------------------------------
8 * This software is supplied "AS IS" without any warranties, express,
9 * implied or statutory, including but not limited to the implied
10 * warranties of fitness for purpose, satisfactory quality and
11 * noninfringement. Keil extends you a royalty-free right to reproduce
12 * and distribute executable files created using this software for use
13 * on NXP Semiconductors LPC family microcontroller devices only. Nothing
14 * else gives you the right to use this software.
16 * Copyright (c) 2009 Keil - An ARM Company. All rights reserved.
17 *---------------------------------------------------------------------------*/
22 /* Device Interrupt Bit Definitions */
23 #define FRAME_INT 0x00000001
24 #define EP_FAST_INT 0x00000002
25 #define EP_SLOW_INT 0x00000004
26 #define DEV_STAT_INT 0x00000008
27 #define CCEMTY_INT 0x00000010
28 #define CDFULL_INT 0x00000020
29 #define RxENDPKT_INT 0x00000040
30 #define TxENDPKT_INT 0x00000080
31 #define EP_RLZED_INT 0x00000100
32 #define ERR_INT 0x00000200
34 /* Rx & Tx Packet Length Definitions */
35 #define PKT_LNGTH_MASK 0x000003FF
36 #define PKT_DV 0x00000400
37 #define PKT_RDY 0x00000800
39 /* USB Control Definitions */
40 #define CTRL_RD_EN 0x00000001
41 #define CTRL_WR_EN 0x00000002
44 #define CMD_SET_ADDR 0x00D00500
45 #define CMD_CFG_DEV 0x00D80500
46 #define CMD_SET_MODE 0x00F30500
47 #define CMD_RD_FRAME 0x00F50500
48 #define DAT_RD_FRAME 0x00F50200
49 #define CMD_RD_TEST 0x00FD0500
50 #define DAT_RD_TEST 0x00FD0200
51 #define CMD_SET_DEV_STAT 0x00FE0500
52 #define CMD_GET_DEV_STAT 0x00FE0500
53 #define DAT_GET_DEV_STAT 0x00FE0200
54 #define CMD_GET_ERR_CODE 0x00FF0500
55 #define DAT_GET_ERR_CODE 0x00FF0200
56 #define CMD_RD_ERR_STAT 0x00FB0500
57 #define DAT_RD_ERR_STAT 0x00FB0200
58 #define DAT_WR_BYTE(x) (0x00000100 | ((x) << 16))
59 #define CMD_SEL_EP(x) (0x00000500 | ((x) << 16))
60 #define DAT_SEL_EP(x) (0x00000200 | ((x) << 16))
61 #define CMD_SEL_EP_CLRI(x) (0x00400500 | ((x) << 16))
62 #define DAT_SEL_EP_CLRI(x) (0x00400200 | ((x) << 16))
63 #define CMD_SET_EP_STAT(x) (0x00400500 | ((x) << 16))
64 #define CMD_CLR_BUF 0x00F20500
65 #define DAT_CLR_BUF 0x00F20200
66 #define CMD_VALID_BUF 0x00FA0500
68 /* Device Address Register Definitions */
69 #define DEV_ADDR_MASK 0x7F
72 /* Device Configure Register Definitions */
73 #define CONF_DVICE 0x01
75 /* Device Mode Register Definitions */
84 /* Device Status Register Definitions */
86 #define DEV_CON_CH 0x02
88 #define DEV_SUS_CH 0x08
91 /* Error Code Register Definitions */
92 #define ERR_EC_MASK 0x0F
95 /* Error Status Register Definitions */
97 #define ERR_UEPKT 0x02
99 #define ERR_TIMOUT 0x08
101 #define ERR_B_OVRN 0x20
102 #define ERR_BTSTF 0x40
105 /* Endpoint Select Register Definitions */
106 #define EP_SEL_F 0x01
107 #define EP_SEL_ST 0x02
108 #define EP_SEL_STP 0x04
109 #define EP_SEL_PO 0x08
110 #define EP_SEL_EPN 0x10
111 #define EP_SEL_B_1_FULL 0x20
112 #define EP_SEL_B_2_FULL 0x40
114 /* Endpoint Status Register Definitions */
115 #define EP_STAT_ST 0x01
116 #define EP_STAT_DA 0x20
117 #define EP_STAT_RF_MO 0x40
118 #define EP_STAT_CND_ST 0x80
120 /* Clear Buffer Register Definitions */
121 #define CLR_BUF_PO 0x01
124 /* DMA Interrupt Bit Definitions */
126 #define NDD_REQ_INT 0x02
127 #define SYS_ERR_INT 0x04
130 #endif /* __USBREG_H */